Conventional television images have an interlaced format. Each image frame typically comprises two fields, each scanned by a predetermined number of horizontal lines. During each field period, only half the horizontal lines in each field are scanned. Typically, the odd number lines are scanned in the first field while the even number lines are scanned in the second field. The two fields comprising each frame are displayed in sequence so that the scanning appears interlaced, allowing the viewer to perceive the full image. Television images that conform to the standard established by the National Television Standards Committee (NTSC) have 262.5 scan lines in each field, thus giving rise to 525 scan lines per frame, with 30 frames (60 fields) per second. The Phase Alternating Line (PAL) standard adopted by some European countries employs 625 lines per frame, with 25 frames (50 fields) per second.
The emergence of high definition television, and more particularly, the High Definition terrestrial broadcast system proposed by the Grand Alliance and described in the 1994 Proceedings of the National Association of Broadcasters, 48th Annual Broadcast Engineering Conference Proceedings, Mar. 20-24, 1994, has led to the development of digital display devices. One such digital display device employs Liquid Crystal on Silicon (LCOS) technology, which utilizes a progressive display format as opposed to the interlaced scanning format used by conventional television receivers. For this reason, incoming television signals having interlaced scanning must undergo de-interlacing before display on a display device that uses a progressive display format. For LCOS technology display devices, the field rate of incoming signals must be changed from the standard rate (i.e., 60 Hz in the United States) to a rate of twice the standard rate in order (i.e., the display signal must under go frame doubling) to drive the LCOS display device with the required sequential reversing frames.
Present-day systems for performing de-interlacing and frame doubling have employed one circuit for de-interlacing and one for frame doubling, usually implemented with two circuits in parallel, with the de-interlacing and frame doubling circuits having separate memories. The use of separate circuits for de-interlacing and frame doubling increases the need for memory circuits.
Thus, there is need for a de-interlacing and frame doubling circuit that reduces the amount of needed memory.